AMD revealed its latest Opteron roadmap last week, debuting sexa-core Istanbul processors and a roadmap around its Maranello platform. Maranello platform is based on Socket G34, a first non-symmetric Socket in recent history. With new Magny Cours and Interlagos CPUs set to feature an 288-bit memory controller and integrated PCI Express controller. A lot of connecting dots…

Socket 1207 or Socket F on the left [Fiorano platform], new assymetric Socket G34 [Maranello platform] on the right. Sorry for the size - but Socket G34 is larger than Socket F.
Socket 1207 or Socket F on the left [Fiorano platform], new assymetric Socket G34 [Maranello platform] on the right. Sorry for the size – but Socket G34 is larger than Socket F.

As you can see on the picture above, Socket G34 is a native dual-die Socket design. It did not conform to all the compromises Intel had to make on the Socket 775 and 771 – but it also makes a mockery out of AMD presentations which lambasted Intel for going Multi-Chip Module.

There you go, now you know how Socket G34 processors look, featuring a quad-channel, 288-bit [64-bit + 8-bit ECC Parity] interface. This socket fits from eight to sixteen cores, available through 45nm Magny-Cours and 32nm Interlagos die-shrink.