On my 28th birthday [August 30, 2007], AMD introduced SSE5 – proposed multimedia instruction set consisting out of 170 instructions. In May 2009, AMD moved to revise the way how instructions were coded in order to ensure compatibility with Intel’s AVX instruction set, set to debut with Larrabee cGPU.

AMD's eight INT pipelines in a single Bulldozer core - SSE5 is all around
AMD Bulldozer’s most distinctive feature are eight INT pipelines per Bulldozer core – SSE5 is all around

Back in May 2009, AMD split the SSE5 into CVT16, FMA4 and XOP. We spoke with Chekib Akrout, Corporate VP at AMD to clarify why SSE5/CVT16/FMA4/XOP instruction sets weren’t mentioned on slides during today?s Financial Analyst Day. In a brief discussion, we asked what is the status of SSE5 as such and when are we going to see the products based on it. Chekib answered that SSE5 will "show up sooner than later."

In a way, we feel that AMD has once more decided to subdue the SSE5 message, which is a shame. Given that Intel plans to introduce the hardware Fused-Multiply-Add support [FMA3] with their 22nm generation [Haswell], AMD’s Bulldozer has a clear lead with FMA4. If AMD opted to show clear "SSE5 in Bulldozer", a lot of things would be more understandable. However, not all SSE5 technologies will make their way in the first Bulldozer, that being Zambezi/Orochi or Interlagos/Valencia.