nVidia is a company that [usually] doesn’t disclose the die sizes of their products. From one side, this has to do with the calculation how much money the company can make on a part, even though the yields and the actual arrangement between nVidia and TSMC is a closely guarded secret. We did disclose the die sizes of the Fermi architecture parts in the past, and now we got a confirmation of those numbers.
From another, in the past nVidia disclosed the die sizes when the odds worked in their favor, as general perception is that the larger die is weakness rather than strength. To us, if a company is able to create a large die in volume, that is a straight testament of excellence from the design and manufacturing teams – Intel’s Itanium or Itanic may not be the biggest commercial success Intel ever made, but the multi-lens manufacturing and the humongous die is where Intel’s manufacturing team gains insight in how to create better gen products.
On GTC 2010, I encountered the Quadro 5000M in its MXM format, outside its usual environment. The heatspreader was removed on the mobile parts and the die was exposed for world to see. For some odd reason, the author of these lines didn’t had a traditional die size measuring unit [quarter dollar], so there was no other chance to compare the part but to play the role of a hobo from the streets of San Francisco.
Luckily, one black shirt member of the nVidia gang saw what I wanted to do and borrowed me a quarter, hence the picture below:
As you can see for yourself, the die is quite big and it lacks a millimeter in height to be larger than a quarter dollar. Oddly enough, there was only one part larger than a quarter dollar: nVidia’s past gen part, GT200 debuted in 65nm variant, and those 1.4 billion transistors occupied 576mm2 of die space.
GF100 launched in 40nm and those 3 billion transistors occupy just a tad less than 530mm2.