Recently, Intel made a big announcement about a breakthrough they made in semiconductor manufacturing technology. Intel proudly presented their new Tri-Gate transistor – also dubbed 3D transistor – which is going to be deployed in the upcoming 22nm process technology. We were invited by Intel to Munich, Germany to see the presentation and then discuss the subject with Intel’s executives and representatives.

On the Left: Conventional Planar Transistor; Tri-Gate Transistor on the Right
On the Left: Conventional Planar Transistor; Tri-Gate Transistor on the Right

Key part of the announcement was the usage of a so called Tri-Gate transistor. In comparison to previous planar transistors, a vertical fin allows conducting channels to form on three sides. In order to improve drive strength multiple connected fins can be employed. This technology is used on top of Intel’s previous silicon innovations like SiGe Strained Silicon first introduced at the 90nm node and High-k Metal Gate which debuted at the 45nm node.

Intel's Transistor Leadership over generations: 90nm, 65nm, 45nm, 32nm and now 22nm. Three major inventions: SiGe, HKMG and Tri-Gate
Intel’s Transistor Leadership over generations: 90nm, 65nm, 45nm, 32nm and now 22nm. Three major inventions: SiGe, HKMG and Tri-Gate

Of course it wouldn’t be Intel if there weren’t a statement from co-founder and Chairman Emeritus Gordon Moore:

"For years we have seen limits to how small transistors can get. This change in the basic structure is a truly revolutionary approach, and one that should allow Moore’s Law, and the historic pace of innovation, to continue."

 

It is important to understand, that the technology Intel announced yesterday will solely be used to improve performance characteristics of the transistors. The 22nm process will enable a 2x increase in feature density, which is exactly what previous full-node steps yielded at Intel. So the Tri-Gate transistor will not affect density at all. At low voltages a 37% performance increase can be observed and a 50% reduction of power consumption at constant performance. The slide published by Intel shows that the Tri-Gate transistor especially improves operation at lower voltages. The weak grey curve in between is what a planar 22nm process would have yielded – according to Mark Bohr a sub 20% gain in performance/efficiency. Thus this innovation provides a performance improvement that is beyond what simple miniaturization would yield.

Tri-Gate Transistor enables lower voltages, resulting in lower power consumption than conventional 32nm Planar Transistor

Tri-Gate Transistor enables lower voltages, resulting in lower power consumption than conventional 32nm Planar Transistor

From an economic standpoint, Intel touts a cost advantage of Tri-Gate transistors over SOI (Silicon-On-Insulator) which is used by GlobalFoundries for their Super High Performance processes, which are currently solely used to manufacture microprocessors for AMD. Both technologies allow the transistor to be fully depleted, which reduces leak currents. While SOI adds 10% additional cost to finished wafers, Tri-Gate only increases costs by 3% for the finished wafer. Intel said that the upgrades needed for their fabs to start manufacturing at 22nm are no more significant than previous technology transitions in the past. Intel said that starting 2011 five fabs will be equipped for 22nm volume production. That includes the D1C and D1D fabs in Oregon, Fab 12 and Fab 32 in Arizona and Fab 28 in Israel. While Intel doesn’t disclose the order in which they will be upgraded, you can bet on the Oregon fabs being first since they are development fabs. Overall the technology announcement doesn’t change any guidance given to the financial community.

Intel's 22nm-enabled facilities: five fabs in Oregon, Arizona and Israel.

Intel’s 22nm-enabled facilities: five fabs in Oregon, Arizona and Israel.

Don’t be fooled by the marketing spin of Intel PR representatives regarding whether they invented 3D transistors or not. During the event, representatives have been upfront, that the underlying ground work was done in cooperation with researchers of other industry heavyweights. But Intel is proud to announce that they are the first company who brings this technology to volume manufacturing of highly complex chips, which is surely no small feat. Indeed we inquired GlobalFoundries about this technology and they replied with "We don?t see the need for these technologies until beyond the 20nm generation." So don’t expect 3D technology from GF to be introduced before the 14nm node. As an aside it should be noted that what Intel touts Tri-Gate transistors are generally known as FinFETs. Intel uses the different moniker to differentiate itself from the competition.
Early 22nm Ivy Bridge Silicon Demonstrated
Another remarkable fact about the presentation was that Intel was able to show actual prototypes of future products manufactured at the 22nm node using the novel Tri-Gate transistors in a working state. This includes notebook, desktop and server versions of the upcoming CPU codenamed Ivy Bridge slated for an early 2012 launch. Actual volume manufacturing of these chips should start in the second half of 2011, thus upholding Intel’s two year cycle with new manufacturing technology.

Of course Intel sees this a bit differently, but personally I had the impression that when touting the competitive advantage of their superior manufacturing technology, it looks like they use that to cover up other deficiencies. Especially Intel’s Atom comes to mind, which looks bad in some aspects when compared to ARM chips. One has to consider that ARM chips are manufactured at 40nm at best with many designs even being at the 65nm node. Intel’s Atom is now moving to the 32nm node and in the presentation even full Atom SOC at 22nm were mentioned. Though when these will be ready for some real action, only Intel knows at this point.

Courtesy of Christian Anderka, Platform Architecture Specialist at Intel Germany, we were able to get some additional info, which will be detailed in the following paragraphs.

Regarding the recent rumors about Apple turning to Intel for ARM SOC manufacturing, we were told that primarily Intel develops its manufacturing processes for internal use. That means that they are not as well documented as processes of other foundries who specifically offer semiconductor manufacturing for other companies. This is due to the fact, that Intel’s in-house design teams can cooperate on a higher level. Foundries like TSMC offer a lot of libraries for design software along with excessive documentation that enable engineers to utilize the technology. Intel has similar tools in-house, but some of it might not be suited for offering them to other companies. Christian pointed out, that in general Intel does not offer foundry services for other companies. However, it doesn’t immediately send companies interested in a manufacturing partnership back home either. In fact Intel actually has announced a partnership with the FPGA vendor Achronix recently.

He also strained that he can’t really say a lot about it, other than the company would have to make a very compelling offer and start cooperating with Intel early on such a project. Due to the circumstance that Intel has a lot of manufacturing capacity; such deals could clearly make economic sense in some cases. Another reason why Intel isn’t exactly asking for customers for its foundries is that Intel considers their top notch manufacturing a competitive advantage which they want to use in order to improve their products in comparison to their competition. Therefore they don’t have the biggest interest in sharing that advantage with other companies. At the end of the day this will probably evaluated on a case by case basis. Regarding Apple we were told to actually ask Apple about it. Christian also said Apple could just take all chips from Intel directly, hinting at a dream of selling smartphone chips to the company. While such a move should not be considered impossible, it certainly looks rather doubtful at this point.

Since Intel just announced using 3D technology on a transistor level, we considered it logical to ask whether they will go 3D on another level as well – or more precisely die stacking. Christian kind of dodged the question by naming some research projects which Intel has announced quite some time ago. In line with Intel’s general policy, no information on specific usage in products was given. Though it was hinted, that if anything, such technology would probably debut in the high-end segment.

When asked about half-node steps, Mr. Anderka pointed out, that such things must be looked at from different angles. When the competition will manufacture at the half node step of 28nm, Intel will already have their 22nm lines in full production. Also developing a process is always a tradeoff between investment and reward. For now Intel’s full node steps aligned very well with their product cycles, so additional intermediate steps wouldn’t make a lot of sense at this point. Generally Intel develops manufacturing processes with some goal in mind, like x% performance improvement or a y% reduction in power consumption compared to a previous generation. Mark Bohr already hinted at the following 14nm step, which is another full node down from 22nm. A technology roadmap published by Intel even shows 10nm as well, so it looks like Intel will stick with full node shrinks for at least two more generations. But at this point Intel made it very clear that they have just announced this major breakthrough at 22nm, so they are clearly not talking about 14nm now.
Intel's P1270 was the codename for 22nm litho process, scheduled for the very end of 2011

When asked how Intel works together with other emiconductor manufacturers on technology development, Christian noted there is already a lot of cooperation in the industry up to a certain point. Intel took the approach to lay the groundwork together with other researchers and companies, but then try to beat them to market at the end of the day. Until now this strategy seems to have worked out rather well, considering Intel is almost a full generation ahead of the competition. But Intel pointed out, that cooperation on some technologies is truly required in order to ensure healthy development of tools or wafer suppliers. For example, there is a joint effort on 450mm wafers. Also while Intel doesn’t provide us with an official timeline, it says that it cooperates with a lot of other companies on getting EUV ready. Industry analysts estimate this lithography technology to be widely used only in 2015.