Soitec announced a comprehensive product roadmap centered on fully depleted (FD) Silicon-On-Insulator technology starting at 28nm and extending down to the 10nm node. They are aiming for the magic 3-way combo: better performance, less power consumption, and cheaper manufacturing.

Soitec FD roadmap
Soitec FD roadmap

One of the main challenges faced by the semiconductor industry is a disappointing cost-benefit ratio, with limited gains in performance and power consumption despite increasingly high development costs. Smaller and smaller transistors challenge fabs and fables s developers.

For reference, a nanometer (nm) is one million times smaller than a millimeter. The number defines the distance between transistors and other components within the CPU. The smaller the number, the more transistors that can be placed in the same area. At 22nm and below, traditional CMOS (Complementary Metal?Oxide?Semiconductor) on bulk silicon is highly inefficient to meet the demands of smart mobile devices. This is because bulk planar transistors have reached the physical limit in controlling leakage current and lack the ability to reduce the operating voltage or dynamic power without compromising performance, a major source of wasted battery power.

We spoke with Steve Longoria, SVP of global strategic business development at Soitec. Longoria gave a high-level overview: FD SOI (Silicon on Insulator) is a CMOS silicon technology specifically designed to operate with very low-power while maximizing performance. Soitec calls this process FD-2D.

AMD has used SOI technology in all of its microprocessors since the launch in 2003 of their K8 CPU. That specific implementation of SOI is known as PD-SOI (Partially Depleted Silicon On Insulator). The technology for fully depleted (FD) is a logical extension of the manufacturing processes needed for tomorrow?s smartphones and tablets.
Planar FD-SOI technology relies on an ultra-thin layer of silicon over a Buried Oxide (commonly called BOx)
Planar FD-SOI technology relies on an ultra-thin layer of silicon over a Buried Oxide (commonly called BOx)

Longoria said Soitec?s FD-2D wafer has an ultra-homogenous and ultra-thin silicon layer as its top layer, enabling it to attain planar FD transistors with silicon down to 5nm under the gate. An ultra-thin buried oxide (BOx) layer with a thickness of 25nm is sandwiched between the silicon base and the top silicon layer. Soitec?s FD wafer flatness is the equivalent of plus-or-minus one-quarter inch over the 1863 miles (2998 km) distance between Chicago and San Francisco.

Soitec FD-2D wafer

Soitec FD-2D wafer

Future generation wafers can take advantage of even thinner BOx layers down to 10nm, paving the way for down to 14nm planar transistor scalability for mobile devices.

Longoria explained that the new technology delivers superior power performance and is cost-competitive with bulk technology. He said all the major fabless companies and foundries have initiated programs to evaluate Soitec?s FD technology. Since Soitec has been a supplier to the Common Platform Alliance Manufacturers, it is safe to guess those manufacturers will be at the top of list to test the FD-2D.

One of the key areas for the fabs and fabless is how to reduce time to create a shipping SoC package using FD-2D. By reducing the processing steps in the example below from 328 to 241, it is clear the cost of manufacturing will be reduced.

FD-2D has fewer processing steps (20 ? 25%)
FD-2D has fewer processing steps (20 ? 25%) 

The SOI Industry Consortium benchmarked 28nm bulk vs. 28nm FD-SOI, so they could make comparisons in silicon of similar IP blocks, such as ARM cores and memory controllers. They found peak performance is comparable with the much leakier ‘General Purpose’ technology, at better dynamic power, and dramatically better leakage power, even lower than what ‘Low Power’ technology variations achieve. STMicroelectronics has a white paper about the process. Their 28nm FD-SOI technology performance is 61 percent higher than comparable bulk technology at 1V (volt) gets even more interesting at lower VDD (Voltage Drain Drain) ? boasting a 550 percent improvement at 0.6V.

Longoria pointed out FD-2D’s key points: fast readiness and compatibility with planar CMOS production lines; no retraining of staff; no new equipment costs; uses existing IP libraries and design tools. He also said FD-2D will not change any of the fabless companies’ proprietary IP ("secret sauce").

In May 2011, Intel announced their Tri-gate or 3D nonplanar transistor architecture (a.k.a. FinFET). Intel is using a variation of the ideas of Chenming Calvin Hu, PhD. Dr. Hu is TSMC Distinguished Professor of Microelectronics at the University of California, Berkeley. From 2001-2004, he was the Chief Technology Officer of TSMC. Dr. Hu?s work has been on transistor designs that substitute the flat channel through which electrons flow with a 3-D ridge, or fin. Intel partners should be releasing their first computers with Ivy Bridge CPU (Tri-gate transistors) during Computex week. This will come about one year after their noisy introduction.

Longoria said Soitec’s fully depleted silicon on insulator answer for finFET is called FD-3D. He said their wafers enable a "fin first" process flow ? fin height and isolation are already built into the substrate. Soitec literature says their ultra-homogenous and ultra-thin silicon layer as its top layer along with an ultra-thin buried oxide (BOx) layer with a thickness of 25nm is sandwiched between the silicon base and the top silicon layer.

Intel Tri-gate vs. Soitec FD-3D for finFET
Intel Tri-gate vs. Soitec FD-3D for finFET

By simplifying the manufacturing process with Soitec FD-3D, you also increase options for manufacturability and overall performance. Longoria said this will reduce development time by one year with simplified manufacturability because their substrate has built-in fin ensuring its geometry control for both width and height. The slide below shows the difference in Intel?s Tri-gate manufacturing process versus Soite?s FD-3D process.

Intel Tri-gate process steps vs. Soitec FD-3D process
Intel Tri-gate process steps vs. Soitec FD-3D process

Longoria said Soitec’s FD-3D has fewer challenging process steps than using bulk silicon starting wafers and typically saves 4 litho steps and over 55 process steps. This means shorter production cycle times for higher productivity and a less likely chance of having finished wafers rejected.

Two of the manufacturers already using Soitec FD wafers are IBM and STmicroeletronics-Ericsson (STE).

Last year, IBM was discussing the advantages of FD-SOI. IBM research manager Bruce Doris said "In the past, there has been a lot of skepticism and controversy whether planar FDSOI could deliver performance. What we have shown is that these planar fully depleted SOI transistors are capable of the drive current needed for high performance applications." Doris added that the SOI community "not only wants low power, but they want some devices with high performance for smart phones and other systems." 

This year at the Common Platform Technology Forum 2012, Dr. Gary Patton, VP, Semiconductor Research & Development Center at IBM and Anna Hunter, VP of Foundry Business for Samsung, both said the road to 14nm process technology means using FD-SOI.

Intel Tri-gate process steps vs. Soitec FD-3D process
IBM will use FD-SOI starting at 14nm

STE is developing FD-2D for LTE. At Mobile World Conference February 28, 2012 in Barcelona, they announced their NovaThor U8540. Using FD-2D wafers, the platform will have CPU speeds up to 2.5GHz, use 35 percent less power which translates into 4 hours more high-speed browsing, 2.5 hours more HD video playback, or an additional full day of use. STE has a 300mm foundry which is just down the road from Soitec in Grenoble, France ? the area known as French Silicon Valley.

STE NovaThor U8540 with LTE
STE NovaThor U8540 with LTE 

Clearly, Soitec’s fully depleted wafers are going to be a game changer for the 28nm node and below. The 28nm process will stay around a lot longer than had been expected and provide greater performance and lower power usage.

Additional reading:
Chenming Hu Welcomes FinFET vs. UTB-SOI Race
IBM Sees Performance from FD-SOI Transistors
Interview With ST-Ericsson’s Chief Chip Architect: SOCs on 28nm FD-SOI ? When, Why and How