The old Federal Reserve Building at 301 Battery Street in San Francisco was the venue selected by Samsung to introduce their R&D foray into Silicon Valley on Wednesday evening. The usual “We are Samsung, we are the world” presentation proved that Samsung has turned into the 800 Pound Gorilla of the semiconductor industry. The company is investing a good deal of money in the San Jose R&D complex on Tasman Drive, San Jose which they’ll be moving into next summer upon its completion. The inclusion of this information in each of the presenters foil set indicates the center looms large in the companies thought processes.

Bob Brennan, Sr. Vice President Samsung Memory Solutions Lab is responsible for research, development and ecosystem teams in the U.S. is looking for more “top talent” to populate cubicles in their brand new R&D facility under construction in San Jose.

Formerly with Intel for nearly 22 years, Brennan is establishing himself as the undisputed lead for Samsung’s memory R&D in Silicon Valley. His former position with Inel was as Lead Enterprise SoC Architect for the “Microserver” product line.

Most of the press/analysts present were disappointed that Samsung didn’t deliver any news on the memory front that would preempt making announcements at the upcoming “Flash Memory Summit” to be held at the Santa Clara Convention Center August 5th – 7th, 2014. Brennan in conversation mentioned they’re saving important announcements for Tuesday’s keynote 12:00 -1:30 PM (August 5th, Tuesday) in which he will share the podium with Jim Elliott, Vice President, Memory Marketing, Samsung Semiconductor.

Reorganizing the Illusion

Samsung’s traditional R&D approach in Korea uses three competing teams to “develop” new product technology that “will go” to market. The winning team enjoys a much improved environment for promotion and other corporate benefits. The losing teams, recycled into the next team effort, are left with a fierce sense to succeed or leave the company to start their own businesses. The approach worked incredibly well during the companies rise to prominence as a memory and now logic foundry supplier. The problem is that most of the “leading edge” technology has disappeared leaving Samsung with the prospect of having to “grow their own”.

Samsung, one of the proverbial Korean Tigers, is now progressing through a stripe change – finding their way in a new role as an international supplier. One in which the company is investing heavily in new fabrication facilities in China. The Xi’an NAND-Flash mega fab in Shaanxi Province, China is scheduled to go online as a standalone fab by year end – all in the interest “of laying the foundation for a more stable supply of memory products to its customers.” One of the items required by China is the proverbial “technology transfer” – China’s way of acquiring expertise in the highly competitive environment of semiconductor intellectual property.
A presentation made by Hong Hao, Senior Vice President, Foundry Business made clear that Samsung is in sharp competition with TSMC. Samsung’s reputation among the fabless user community suffered a major setback when Apple withdrew their business – Samsung had decided to compete with their customers. Hong, a graduate of the University of Science and Technology of China (BSEE) and Stanford University (MSEE, PhD) has the right credentials for upward mobility in his position at Samsung.

BSN* Take

Samsung is caught between sustaining growth and meeting customer demands without competing with them. Just how far the company can take vertical segmentation without losing their high volume customer base is in question. Additionally they are persona non grata at the IP font of new product development forcing the company to invest in an institution in Silicon Valley whose mission is the discovery of mass markets that will fill the company’s massive fab investments.

Samsung appears to be leaning toward favoring their China business operations in the interest of low cost mass production to supply the company’s increasing vertical market interests – this may help explain the lack of 3D NAND-Flash devices outside of samples. Might this be the subject of a major announcement at the upcoming Flash Memory Summit?