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Wednesday, June 19, 2013
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Comments
And the winner is by: Sean Kalinich on 11/10/2009
The real problem is the state of company PR and FUD.

You see while all of the items you bring up are true the average consumer (and even many enthusiasts) do not know that making changes to the chipset changes the entire layout (traces etc) of a mainboard.

They also do not know how difficult it is to rework a chipset to add something like USB 3.0 and SATA 3.0 into it.

Due to this lack of common knowledge companies can bad mouth each other and expect a consumer uproar. If the company is not popular (like Intel is at the moment) then it becomes even more effective.

As far as cache on a SATA 3.0 or SAS 2.0 controller goes they actually slow down the I/O speed of SSDs because they are slower than the drives themselves. LSI and Areca recommend turning off all Caching if on their controllers if you are using SSDs.

In the end the current migration path for both USB and SATA 3.0 are the same as they have always been, discrete third party controllers at first then integrated into the chipset later. Nothing new or nefarious going on here, unless you count the NV FUD being thrown out to show how Intel is bad for not allowing them to make chipsets for their new 1366 and 1156 CPUs, and how much better NV chipsets are than Intel's...

But then again that is nothing new either is it...
Here's a theory... by: Toby Hudon on 11/9/2009
I've got a theory regarding USB 3.0 and SATA 3.0 (is it 3.0 or is it just 2.5 @6Gbps? Let's not repeat the "OMG SCSI-3!!!" fiasco if possible?) The issue is likely a problem of interconnect to the chipset.

If Marvell and NEC implement the spec on chips, and those chips are crippled by the lack of available bandwidth to the rest of the system, well then in Intel and AMD's book it's not their problem. But if the ports are implemented as part of an integral chipset, then they have to regard complaints of crippled performance as legitimate.

USB and SATA are commonly implemented in pairs. With 480mbps USB 2.0 that's about 1Gbps per header, and with 3GBps SATA it's obviously 6GBps per pair. PCIe 2.0 spec is 5GT/s with 20% 8/10b encoding overhead so effectively 4Gbps of bandwidth (500MB/sec). Throwing a few USB 2.0 ports on an x1 PCIe 2.0 link is no problem, and you can get away with a pair of 3GBps SATA ports or more since the scenarios for sustained peak throughput on more than one were pretty rare before the advent of low cost high end SSDs. I.e. not even RAID0 would likely hit it due to spindle speed variance and sector reassignment causing desynchronous stripe read timing.

But USB 3.0 and 6GBps SATA with SSDs changes the ballgame completely. Now the x1 PCIe 2.0 bus is insufficient for more than one USB 3.0 port, and can't hack it for even a single channel of the new SATA standard. Which wouldn't have been a problem with standard hard drives as the port interface has regularly outpaced sustained transfer rates by a good margin, giving plenty of time for potential bottlenecks to solve themselves via Moore's Law before disk speeds closed the gap. But the rise of SSDs has changed the game. They've already been bumping into the interface speed limit for some time. 6GBps ports will make the bottleneck in the port->chipset links apparent, and likely cause complaints from consumers who can't get a significant performance boost from newer hardware. It's pretty obvious that if Kingston's 40GB 5 channel "boot drive" can peg 3GBps SATA at the limit on reads, that the standard 10 channel Intel SSDs should have little problem demonstrating a huge performance boost from a move to 6GBps. But if Intel updates them to that standard and their performance doesn't increase significantly, people will figure out the issue. If the problem was confined to their own drives, they could just manage it on that side, but with competitors in the same speed class they have no choice but to keep 6GBps out of the chipset and then blame the lack of performance increase on the third party chips.

The "obvious" solution is to put USB 3.0 and 6GBps SATA controllers on multiple PCIe lanes, right? But this would mean a reassignment of board traces and a reduction in lanes available for the slots. And in some cases (Core i5 for example) those lanes are a pretty scarce resource. An "enthusiast" board with 6GBps support but no ability to do SLI/Crossfire will just be shooting itself in the foot since the early adopters who can afford one are the same who demand the other, and a compromise will just get the product a bad reputation.

So for now we're stuck with 3rd party chips that are hampered by the older bus. When PCIe 3.0 comes out we should see chipsets with onboard USB 3.0, 6GBps SATA, and I'm guessing even some form of 10GB ethernet over CAT6 by then. Since that spec is expected to finalize in Q2 2010, the chipsets aren't likely to be done till Q3 2010 the earliest. Hence the delay.

Will someone attempt to beat Intel and AMD to the punch with a proper chipset with more lanes? If Nvidia was still in the game I'd have said maybe. But with them retiring from high end motherboard chipsets to focus on Ion and Tegra, I doubt we'll be seeing VIA or SIS or anyone coming out with this feature.

So save up for a decent 6GBps Areca or LSI (now that they've bought 3Ware) card, and expect more products like the OCZ Z-drive for the next year, because it's the only way storage read performance is going to be increasing at all. Also expect some "cheating" numbers that focus on burst performance that has no value in the real world, and maybe something sneaky like a tiny bit of cache on a 6GBps controller itself to get those scores.
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