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Saturday, March 20, 2010
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Comments
by: Anonymous on 7/22/2009
2 Cores in 1?
I have been reading around the web about Bulldozer and this seems as appropriate a place as any to post what I think is happening.
Now I think we have all read the rumours about Bulldozer being a Floating point monster and how it is suppose to be able to allow a thread to execute across 2 cores if the need arises.
What AMD seemed to have said is that, 80% of all instructions can execute quite happily on 2 integer pipelines and that the FPU is not used most of the time, but this is what Via aim at with their CPU’s and not what we expect from AMD.
Is it a dual core or a dual thread single core? Imagine a design that has dual 2 pipeline integer cores that are equally happy working as 2 processors as they are 1 large 4 pipelines integer unit! 80% of the time a thread is able to stay on the smaller “core” but 20% of the time the 2 “cores” merges to become an integer processing monster. Very cleaver really. In addition, the FPU will process 2x128 bit instructions at a time or 1x256 AVX instruction per cycle, with this FPU being shared by both the smaller “cores”. I refer to the integer “cores” in quotations because in a diagram they could look like a wide single core processor with the L1 caches to support 2 concurrent threads though marketing will probably claim what this is a dual core processor, and a quad core processor would have 2 of these 2 in 1 processors. Such a design would make it much easier to power down large sections with none to negligible impact on performance.
All this is just speculation on my part from what I have read here and there, and if I am even close to being correct, then I am very impressed and am chomping at the bit to buy one of these. I can hardly wait!
by: Anonymous on 7/7/2009
As AMD are now going to utilise Intel's AVX instructions (and a good thing too), it is more likely to be a 256 bit monster. What is most likely is to see intrruction fusion, vastly increased instructions "inflight" and larger and/or reduced latency cache, which was "sugested" by Fred Webber from an interview of a few years back (sorry I couldn't refind the web link).
Not sure about all of this. by: JF-AMD on 4/23/2009
(copy and paste from my comment on AMDzone that pointed to this article...)

I want to be totally upfront here. I am an AMD employee (and blog frequently for AMD).

Here at AMD we take a lot of pride in our products and we take our confidentiality very seriously. For strategic reasons we don’t comment on future direction, regardless of how valid (or invalid) it is, so I don’t want to get into a discussion of the technical details of the article.

The only 2 points that I wanted to bring up are:

1. The original article states: “According to our sources, this is one of the problems in Bulldozer design - it isn't easy to design a FPU, especially when you have to put engineering resources to fix the Barcelona core and shuffle scientists around.” This statement, frankly, is short-sighted and inconsistent with where AMD has been executing. “Shanghai” which was supposed to launch in early 2009, actually launched in November of last year. “Istanbul” was supposed to launch in the second half of this year and is now launching in June 2009. “Magny-Cours”, originally a mid 2010 product is now scheduled for Q1 2010. Hardly the picture of a company that is struggling with resources and behind.
2. The charts that were used are horribly old. Not saying they are correct and not saying they are incorrect, just very old.

Combined it makes me wonder where the details are in fact coming from, which brings the conclusions drawn into question. So I invite readers to draw their own conclusions.

AMDers have high confidence that our server strategy will help differentiate us in the market and allow us to more uniquely address customers’ needs. Just like we did with the original AMD Opteron and just like we plan to do with the 2010 products.

Don’t want to be a tease, but that is all I can say. Check the news, we made a series of big announcements today.
Re: No wonder... by: fellix on 4/17/2009
The FP/SIMD implementation in Barcelona and Deneb cores is still pretty much intact from what was found in the very first K8 (even K7, to be honest). What the difference is here, is that AMD's engineers just slapped a second 64-bit FPU block along with the existing one, while only the front-end and the retire paths were re-designed to handle single-cycle 128-bit op's.
Such solution is just a quick and easy way to patch upon, but quite inefficient (resource wise), compared to a native approach, as there's quite a lot of logic redundancy.
No wonder... by: YMF1 on 4/16/2009
...that no one really considers Theo Valich seriously.

" A good example will be the newly designed 128-bit FPUs [Floating-Point Units]. Currently, 128-bit instructions are carried out by using 32-bit / 64-bit FPU at a reduced efficiency [more cycles needed to process a single instruction]. According to our sources, GPR [General Purpose Registers] were increased to 128-bit. Once that we learned of this alleged GPR depth, we asked does that mean we can, theoretically, call Bulldozer a "128-bit CPU" and is "x86-128" on the way? I will openly admit that I asked such a question without giving it a second thought."..

But, according to RealWorldTech on Barcelona,

"The FPUs in Barcelona did change a bit. They were widened to 128 bits so that SSE instructions can execute in a single pass (previously they went through the 64 bit FPU twice, just as in Intel’s Pentium M). Similarly, the load-store units, and the FMISC unit now load 128 bit wide data, to improve SSE performance."

Oh crap. Does that mean Barcelona is a X86_128 number crunching monster too? OMG!!

Wait! It doesn't stop there! According to RWT on Core 2...

"Core has three execution dispatch ports, which feed a total of three 128 bit SSE units, two 128 bit floating point units, and three 64 bit integer units."

Oh wait, that means Core 2 is also an x86_128 CPU! Wow, have we really enter into the 128bit computing era?

Seriously Theo, the 128bit FPU has been long implemented. Stop hyping something out of nothing.
Late again huh? by: General Lee D. Mented on 4/15/2009
I keep hoping to see AMD actually pull ahead again and make Intel work a little harder but it just doesn't seem in the cards.

Though right now I'm more worried about the graphics situation. I'm pissed off at ATI's crashy drivers, and at Nvidia's buggy hardware. But where else can you go?

BTW "we get - eight completely new architectures, improved numerous times. Out of those seven," on page 1. ;)
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