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Wednesday, May 22, 2013
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Comments
Umm... by: General Lee D. Mented on 5/7/2009
With regard to the previous comment, "clock speed will increase power usage by a factor of 8 as per Los Alamos National Labs. http://www.lanl.gov/news/index.php/fuseaction/1663.article/d/200805/id/13277":

The quote by Ken Koch "With transistors at 65-nanometer sizes, the heating rate would increase 8 times whenever the clock speed was doubled, outstripping our ability to carry the heat away by standard air cooling." is referring to the leakage problem, not actual power consumption calculation. This is one of the big deals about Intel's hafnium-based process, reducing leakage.

IC power is P = C x V^2 x F where C is capacitance, V is voltage, and F is frequency (leakage is ignored in this equation). Power scales linear with frequency, but squares with voltage. This is why overclockers can't just throw more and more voltage at a CPU and keep increasing the clocks. Eventually more voltage is working against you rather than for you. Improving cooling allows for a higher tolerance of voltage increase, hence why watercooling and liquid nitrogen allow such high overclocks.


On a related note, hey Theo have you seen these E0 stepping Core 2s? I finally got my E8500 up and running and it's stable at 4222 (9.5x444 which gives you a 1066 mem divider) at stock voltage! And that's on a 92mm air cooler! I haven't even tried to really squeeze it yet, not bad for a sub-$200 chip and $30 cooler huh? ;)
No surprise by: Sandia-X on 5/6/2009
For those familiar with the Superpetaflop competition begun in late 2002 by DARPA the performance of this chip is no surprise. NITRD http://www.nitrd.gov/pubs/2006supplement/hec_rd.pdf picked this cpu along with the IBM P-7 as the winners back in 2006. DARPA eliminated Nehalam in the first round of the competition. Linpack really isn't the benchmark you would want to test this with. The DARPA HPC Challenge is a better benchmark as per Jack Dongarra (author of Linpack). http://www.netlib.org/utk/people/JackDongarra/PAPERS/adv-comp-darpa-08.pdf The paper also compares the Cray/AMD MTA-2 architecture with Intel's RDMA based architecture (explaining why an AMD dual core X2 is faster than an Intel quad core per socket when the going gets tough http://bebop.cs.berkeley.edu/pubs/williams2008-multicore-lbmhd.pdf) and gives a brief history of life at the cutting edge. Reading this paper to be presented in Rome later this month http://post.queensu.ca/~afsahi/PPRL/papers/HPCS08.pdf Intel will need a complete restructuring of the design to eliminate inefficiencies and compete with AMD and IBM the high end. One note on the overclocking though administrators need to be aware that doubling the clock speed will increase power usage by a factor of 8 as per Los Alamos National Labs. http://www.lanl.gov/news/index.php/fuseaction/1663.article/d/200805/id/13277 Personal guess is that by the time Intel can get to 1 petaflop, IBM and AMD will be near 6 petaflop target for the Superpetaflop project. Desktop benchmarks simply lack the sophistication to challenge the design of this cpu.
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