The ARM Techcon03 conference in Santa Clara, California - opened with nearly two hour session about optimizing the ARM IP for next-generation, 32/28nm LP [low power] mobile SoC [silicon on a chip] designs. The Common Platform [IBM, Chartered Semiconductor Manufacturing and Samsung Electronics] Alliance and ARM explained physical and processor IP and tool/flow solutions for the Common Platform’s 32nm/28nm high-k metal-gate [HKMG] process technology.
One of the more interesting slides showed 10 samples of ARM's 32nm evolution. A year ago the ARM Cortex-M3 was the first test chip. Over the months, eight more examples were tested [taped out, tested, analyzed]. In August, the first 28nm test chips showed up. They gave invaluable insight into the trade-offs when reducing from a 40nm fab process. This month ARM and the Common Platform Alliance begun working on optimizing the Cortex IP for the processes at hand.
ARM Table: Development of 40nm, 32nm and 28nm process over the course of last couple of years
ARM and Synopsys said that by the end of 2010 ARM 32nm LP chips will be shipping to the mobile device manufactures. That means we will be seeing very fast, low power smartphones and smartbooks / netbooks. This will happen because the ARM IP core and their licensee chip designer are now working directly with the fab house implementing low-power/low-leakage, HKMG process technology.
The primary objectives of this collaboration are to reduce risk and design cost, and improve time to market for advanced mobile products by taking advantage of developments in material science, processor architecture and physical IP, mobile multimedia implementation and SoC design. ARM explained the gains they made going from 45nm to 32nm. During ARM's testing process of similarly configured test chips, they found there was a 55 percent reduction in the chip size. They also discovered a 30 percent decrease in dynamic power consumption and a 43 percent decrease in leakage, along with a 24 percent increase in frequency.
Benefits of smaller manufacturing process are very impressive - 55% die savings with 43% reduction in leakage
At the ARM booth for Cortex-A5 and A9, we saw some interesting demos devices. An A5 demo unit was aimed at the low-power, lower cost devices. That A5 was a single core test CPU with Mali-55 GPU in an SoC running the Android OS. This would be a perfect combination for an MID. The A9 Quadcore test CPU had each core tied to an LCD display that light up when each core was being used. The engineer explained that the Cortex-A9 MP IP designed as a Quadcore SoC running in high performance mode at 2GHz would be able to take a 4-threaded application and handle it like a mid-range desktop X86 CPU does. The Cortex-A9 MP will be the first ARM IP to move directly to the next-generation, 32nm/28nm LP mobile SoC. We also learned that a Quadcore Cortex-A5 on 40nm will have about the same power as a dual core Cortex-A9 40nm running at 1GHz.
From what we can see following this interesting session, ARM worked in silence on the daunting task of shrinking the Cortex IP and got some interesting results in process. While 55% die reduction was expected as far as processing geometry goes, 43% decrease in leakage prompted ARM to start experimenting with IBM and GlobalFoundries and recently demonstrated ARM chip manufactured in SOI [Silicon-on-Insulator] process. With expansion from bulk silicon to SOI and remarkable performance achieved with both bulk and SOI silicon, ARM customers can be spoiled in their choice of manufacturing facility. This British company is swiftly moving forward and unless major hiccup occurs, there is little doubt that Qualcomm, Samsung, Texas Instruments, nVidia and others will be quite satisfied. We'll continue to closely follow the development in the field.
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