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Friday, November 20, 2009
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AMD's 8-Core Valencia and 16-core Interlagos are based on Bulldozer



Pat Patla, AMD's VP and General Manager of AMD Server and Workstation business recently had a conference call explaining the progress AMD is making on the server and workstation front.

AMD is of course, ecstatic about the Istanbul, its sexa-core server/workstation processor. The company is bidding on Istanbul buying enough time to prepare Socket C32 [Opteron 4000] and Socket G34 [Opteron 6000] processors, the key ingredients of the AMD Maranello platform.

Pat sounded off confident in the strength of the line-up, praising socket compatibility and easy drop-in infrastructure. This is one of the issues we had, since touting the existing infrastructure isn't going to win a lot of new customers, who all know that Maranello and Socket C32 and G34 are on the way. Currently, in the battle of sexa-cores, there isn't much to write home about - Istanbul trumps Dunnington and there isn't much to say about that on the blade server space - where virtualization and cloud computing dominate. When we look at Nehalem-based server chips, AMD knows that it has to push the price/performance ratio and the existing infrastructure, since quad-core Nehalem-EP and octal-core Nehalem-EX will give serious run for the money. Of course, we haven't forgot about 32nm sexa-core Westmere, a Xeon 5600/Core [i8? i9?] processor that is scheduled to debut before year's end.

According to Patrick Wang, senior Semiconductor analyst over at Wedbush Morgan, AMD Istanbul carries "compelling price points when compared to Shanghai and Intel’s counterparts. Specifically, when compared to Shanghai, an Istanbul-based server could deliver ~50% more cores at only a ~5% increase in cost (or ~3x less than Nehalem-EP)."

AMD will be on the defensive until 2011, when the infrastructure [Maranello] will be in place for the arrival of Bulldozer-based processors. For now, AMD has to push the Broadcom and nVidia powered Santa Rosa and AMD's own upcoming Fiorano server/workstation platforms.

AMD Commercial Roadmap with Maranello platform, Magny-Cours, Interlagos CPUs
AMD Commercial Roadmap with San Marino and Maranello platforms and Bulldozer-based Interlagos and Valencia CPUs

Enter Interlagos and Valencia; AMD's first processors based on the revolutionary [for AMD, of course] CPU architecture. According to released information, a 170% increase in number of cores [from 6 to 16] should result in 400% performance increase in Floating-Point calculations on a clock-per-clock basis. Add variant clocks to that and we have a receipt for a hard battle in server/workstation segment. Valencia's theoretical numbers should show similar jumps, but overall performance will differ due to difference in memory controller: Valencia comes with a dual-channel, 144-bit memory controller while Interlagos features a quad-channel, 288-bit memory controller.

According to the call, it can be expected that Bulldozer will be a seriously big deal for the CPU space. While Bobcat targets the low-end and wants to go after spreading ARM and its Cortex series, Bulldozer is the first new CPU architecture for AMD since Hammer series in 2003. While Patla wasn't willing to disclose interesting architectural details that would explain the impressive jump in projected performance for the Bulldozer-based Interlagos processor.
What makes this scenario realistic is the fact that after all the situation we had with the former CEO, Dirk Meyer is making sure that the company stopped missing its own roadmap, causing the stocks to drop to $4.19, at the time of writing. The lowest point was 1.62 USD, a disastrous drop from $44 of yesteryear. Shanghai was launched around one month early, Istanbul was launched five months early and this is a far cry from over a nine months delay with Barcelona [first roadmap leak to product release, not counting all those modified roadmaps].

Here at BSN*, we ran a story based upon our information about the Bulldozer architecture and somehow the projected performance would fit the bill of massive changes inside this 128-bit architecture. We also disclosed the architecture of Magny-Cours. With the built-in HT Assist in its second generation, performance scaling should prove to be quite impressive, just like AMD Athlon K7 blew existing K6-2 and K6-III out of the water. If you're confused with all the codenames, we ran a story revealing the AMD's codenames a while ago.



© 2009 Bright Side Of News*, All rights reserved.



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IP address change delay

Greetings,

The planned network provider change will not happen as planned, due to our site administrator ending in hospital as a consequence of his gliding accident. The wounds are not life-threatening but Mr. Ivica Hosko is still in the hospital, four days after the crash with transportation to Zagreb in two days time. We send our best wishes and hope for a speedy recovery. As soon as Mr. Hosko returns to his daily post, we'll announce the details of our network provider switch.

The following message is for Mr. Ivica himself:  "Ivica, you nut - gliding around a 2km/6600ft mountain with changeable winds in November?"

Thanks for understanding,

Ed-in-chief

© 2009 Bright Side Of News*, All rights reserved.