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Friday, November 20, 2009
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Intel to demonstrate a 32nm Core i9 CPU in September



While the media is previewing P55-motherboards featuring LGA-1156 socket for the upcoming 45nm quad-core Lynnfield processors [Core i5-700, i7-800 series are all set to launch in the first week of September e.g. next week], it is little known that Core i9 1000 will make a public appearance in September as well. During the upcoming Intel Developer Conference 2009 [September 22-24, San Francisco's Moscone Center], Intel plans to publicly demonstrate the 32nm processors, with the accent on the sexa-core, duodec-thread Gulftown.

Gulftown processor will use the LGA-1366 socket, already a home for the current Core i7-900 series of processors, so Gulftown will continue to feature 216-bit [64-bit +8-bit ECC per channel] triple channel DDR3 memory. But what makes Gulftown so special is not the fact that this processor does not belong to current Nehalem architecture – this is the first member of the Westmere architecture [the 32nm "tock" in Intel's Tick-Tock cadence]. Westmere processors come manufactured in the 32 nanometer process, and feature native dual, quad, sexa and octa-core designs.

Intel decided to name processors from Core i9 series with a 1000 suffix, a logical step from Core i5-700, i7-800, i7-900 and now - i9-1000 series. According to the sources in the know, 32nm has some trouble achieving good thermals for the planned Turbo architecture and dynamic clock scaling. The goal is to bring this even further than in 45nm Lynnfields. Once that thermals are in the desired range, Intel will target aggressive clock scaling for its desktop parts [Gulftowns from Xeon 5600 series will be more moderately clocked and fit inside workstation/server TDP's]. Regardless of when it happens [Q4'09, we would place our bets on November], the upcoming arrival of a sexa-core processor to desktop probably will force the competition to either enter the sexa-core arena on desktop [Phenom II "X6" or rebranded Opteron 1400 series], or stay aside while Intel reaps the positive PR and more importantly, gather developer support.

Note that we are using the proper latin prefix "sexa" for describing a six-core processor, unlike the official line from both Intel and AMD - that will switch to greek and use prefix "hexa" [in that case, dual-core and quad-core would be di-core and tetra-core], afraid of using anything that has "sex" in the name, even though english number six derives from latin's number "sex". Then again, we all know how corporations and especially majority of Americans are paranoid about that three letter word. At BSN*, we'll continue to use the written sequence until 10-cores, after which we expect that all media wilswitch to "XX-core" naming convention anyways.

In any case, there is little doubt in our minds that Intel is doing nothing short of an excellent job and keeping the crown as the manufacturer of highest-performing x86 processors in the world.


© 2009 Bright Side Of News*, All rights reserved.



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Comments:

doudec - dodeca by: Anonymous on 8/26/2009
following the "official"(greek) line all 12-cores should be called dodeca-cores.
If only... by: Anonymous on 8/25/2009
they weren't such a cut throat, squash their own friends kind of company. I would never buy an Intel chip for personal use.
They even crapped on a non-profit.
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IP address change delay

Greetings,

The planned network provider change will not happen as planned, due to our site administrator ending in hospital as a consequence of his gliding accident. The wounds are not life-threatening but Mr. Ivica Hosko is still in the hospital, four days after the crash with transportation to Zagreb in two days time. We send our best wishes and hope for a speedy recovery. As soon as Mr. Hosko returns to his daily post, we'll announce the details of our network provider switch.

The following message is for Mr. Ivica himself:  "Ivica, you nut - gliding around a 2km/6600ft mountain with changeable winds in November?"

Thanks for understanding,

Ed-in-chief

© 2009 Bright Side Of News*, All rights reserved.