Intel's "Anti AMD Fusion" Sandy Bridge CPU tapes out
7/5/2009 by: Theo Valich
French site Canard PC revealed a picture of a successor to the upcoming Intel's architecture, successor of Nehalem and Westmere, its 32nm die-shrink. Under the codename Sandy Bridge, Intel is preparing its architecture that will go head-to-head against AMD's allegeldy revolutionary Bulldozer architecture.
Sandy Bridge architecture will be the second architecture to incorporate 256-bit AVX instruction set [Advanced Vector Extensions], the first one being Larrabee, Intel's upcoming cGPU.
Sandy Bridge also features built-in AES [Advanced Encryption Standard] encrypting engine, VMX Unrestricted feature for the VMX engine [Virtualization Machine eXtensions http://en.wikipedia.org/wiki/X86_virtualization]. From the already familiar features, you'll be happy to hear that Turbo feature will remain on for generations to come, while Hyper-Threading should provide some sizeable performance improvements.
The screenshot shows the future of Intel: CPU+GPU, starting off with allegedly-GMA based DirectX 11 compliant GPU , quad-core CPU and a lot of cache. Picture courtesy of Canard PC.
Each of Sandy Bridge cores comes with 32KB of L1 Data cache, unknown amount of L1 Instruction [same?] cache and 256KB L2 cache. L3 cache should vary in size between 8-24MB, depending on the processor in question [desktop CPUs should range from 8-16MB]. What's noticeable at first is the increased latency of the SRAM memory in question and a dire reminder that electrons no longer travel at the speed of light. L1 cache is now three cycles away, L2 is nine cycles away, while L3 cache is full 25 cycles away.
The French site claims that the CPU based on Sandy Bridge architecture already taped out, in the final week of May 2009. The taped out part is a successor to Clarkdale/Arrandale, 1st gen Fusion CPUs from Intel. Canard PC also claims that this Sandy Bridge quad-core + GPU chip doesn't feature a Larrabee core, something that is open to speculation. If the rumor that IGP is connected to L3 cache proves to be true, we have little ground not to believe that it is either the final step before Larrabee integration, or a first generation Larrabee CPU+GPU part.
The taped out CPU also contains 20 PCI Express 2.0 lanes and a DMI interconnect. Advanced power saving features could result in overall system consumption of just 18 Watts in idle, as one of Intel's Senior Performance Engineers disclosed in a public forum.
Four cores should tick at 4GHz, while the IGP will tick anywhere between 1-1.4 GHz. The die size is estimated at 225mm2, consuming 85W of juice. The expected rollout is scheduled for the first quarter of 2011, just in time for the debut of AMD's Bulldozer and its Llano Fusion CPU.
According to AMD's public roadmap, this Sandy Bridge CPU is already looking good on paper, with Llano featuring four Bulldozer cores and "only" 4MB of L3 cache. Both parts will feature the same DDR3-1600 memory interface, offering 25.6 GB/s of system memory bandwidth.
Intel hopes that this part will be enough to take on AMD, but if the GPU is not based on Larrabee, we don't see any hope for a decent DirectX 11 implementation on Intel's side.
The Sandy Bridge line-up will also feature sexa-core and octa-core with 16 and 24MB of L3 cache memory, as well as lower-end parts with only two cores. Please do note that this article is looking 16 months in the future and even this first tape-out doesn't mean that the architecture is cast in stone… but it proves Intel's engineering brilliance, taping out a CPU architecture that isn't supposed to come out to market for the next year and a quarter.
Intel, Intel corporation, Core, i3, i5, i7, Nehalem, Westmere, Sandy Bridge, 45nm, 32nm, dual-core, quad-core, sexa-core, octa-core, octal-core, AMD, Bulldozer, AVX, Advanced Vector Extensions, AES, Advanced Encryption Standard, VMX Unrestricted, VMX, cache, L1, L2, L3, Clarkdale, Arandale, Larrabee, LRB, cGPU, CPU+GPU, Fusion, IGP, GMA, DirectX 11, DX11, Llano, Orochi
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