IBM set to release first public information on POWER7
8/21/2009 by: Theo Valich
This weekend, The Sheraton Hotel in Palo Alto is hosting Hot Chips 21, high-level conference bringing details of new developments in the world of chips. According to David Kanter of RealWorldTech, the star of the show should be IBM's first public disclosure of POWER7 architecture.
IBM has two presentations, one should focus on the architecture itself, while the second one should address the system interfaces. Currently known information about POWER7 is nothing short of amazing: both IBM and Intel did a wrong turn with previous architectures [IBM - POWER6, Intel - NetBurst e.g. Pentium 4], focusing on high clocks instead of efficiency. But unlike Intel, IBM's designs achieved launch speeds of 3.5, 4.2 and 4.7 GHz, and the POWER6+ upgrade brought the 5.0 GHz clock.
IBM's POWER6+ in Multi-Chip module package - 5.0 GHz, octa-core design with off-die L3 cache
If you recall, IBM's Cell was supposed to work at 4.0 GHz, and two of them were supposed to be the base for PlayStation 3. Ultimately, Cell hit a clock wall at 3.2 GHz [interestingly though, Intel hit the thermal wall at the identical 3.2 GHz clock] and nVidia came into picture with re-designed GPU codenamed "NV47/RSX" [We all know that NV47 was GeForce 7900GTX].
Getting back on the subject of POWER7, IBM plans to use eDRAM memory for its L3 cache, and that is without the doubt - presedan in the world of CPUs. If eDRAM does good on this low-volume high-performance architecture, given its high density - we could see AMD and Intel moving from SRAM to eDRAM for their caches, almost tripling the capacity of their caches for the same die space.
Imagine Intel Core i7 with 24MB of L3 cache by using eDRAM instead of 8MB SRAM - 24MB would do nicely for a native 12-16 core design without cache starvation.
According to the information we have, POWER7 should debut as an up to octa-core design at 4.0 GHz clock and serve as a base for next generation of BlueGene HPC architecture - BlueGene/Q.
IBM, Hot Chips, Hot Chips 21, Sheraton, Sheraton hotel, Palo alto, IBM, Power, Power6, CPU, power efficiency, thermal efficiency, P4, NetBurst, Power7, microarchitecture, David Kanter, Real World Tech, Real World Technologies, eDRAM, FO4 delay, L1, L2, L3, cache, dual-core, octa-core, BlueGene, BlueGene/Q
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