Flash Summit 2010 - Newcomer Changes Everything?
8/30/2010 by: Gil Russell
Last year was a good year for SSD’s in the Server environment. Everything was coming up roses till it became clear that one company had been dissembling their capabilities to some rather large storage players. Things rapidly fell apart with many reputations irreparably tarnished. The market darlings turned into the shunned and avoided. Come forward one year and the situation has further deteriorated; a lengthening recession; Flash supply/price instability; declining duration values; has stalled any forward motivation in the adoption rate.
There is one company happily advancing along their own Flash storage roadmap, Apple. Not showing, nor sharing their internal technology has worked well to leverage their products. This is managed technology - integrated to amplify a products utility to the user. Apple is a company that innovates through the art of brilliant thinking. They are an example of SSDs launched successfully and help illustrate that the problem is not with Flash technology but the way in which industry has managed it.
Flash as a Noisy Communications Channel
The notion of flash memory as a noisy communications channel is a rather recent development. ECC capability has been an established industry DRAM standard to detect and repair errors. It was naturally applied to flash to improve raw error rates to an acceptable level. The shrinking geometries along with the pressures of packing more information per cell in an effort to reach price per bit economies is resulting in an escalating raw bit error rate requiring that the number of bits to correct the data is now becoming a significant overhead factor [a vicious circle].
Hard disk drives have long used forward error correction codes that include Viterbi, Hamming, Reed-Solomon and BCH codes. Turbo and Low Density Parity Codes are relatively recent additions that provide optimal Shannon Limit channel efficiencies. LDPC has assumed lead position and is quietly being offered by several well known IP companies involved in supplying the flash sector.
LDPC is extremely compute intensive resulting in a high power budget and increased latency. Some of the vendors claim that they’ve been able to overcome or adjust the code for much improved power efficiencies though this remains to be seen.
The Importance of LDPC to the Flash Memory Producers
As mentioned the shrinking geometries and the packing of more bit levels on each cell is resulting in a technical diminishment of the memory reliability function and is somewhat difficult to defend without some sort of minor miracle to restore it. Enter LDPC. When managed correctly the technology can transform duration and bit error reliability of MLC and TLC to the reliability levels of SLC NAND-Flash. The producers have little or no choice but to use it.
Lyric Semiconductor, an Incredibly Well Timed Debut
It is not often that a start-up technology arrives on the scene and changes everything overnight. Lyric Semiconductor made their debut out of stealth mode at last week’s summit.
Advanced ECC via LDPC or how to save all the data on the flash drive, not 999 out of a 1000 bits.
Lyric received early funding through DARPA grants to the tune of $20 million. It seems they’ve been looking at Bayesian Networks which are used as probability filters that predict probable outcomes from indeterminate input values. The company has put this theory to practice in the form of a LDPC error correction device that uses analog values to set node weights within a Bayesian filter network. Suffice to say it does LDPC at extremely low power [10x lower] and at very small silicon size [30x smaller]. Lyric demonstrated a working system in their suite running a TLC NAND-Flash based USB drive.
Lyric has filed for 50 Patents to date and is funded by Stata Venture Partners and has Ray Stata, founder of Analog Devices, is Lead Investor and Chairman of the Board. Home offices are located in Cambridge, Massachusetts.
The adoption of the EZ Flash Interface released in the ONFI 2.3 specification [announced at the summit] allows for an easy integration path for Lyric’s technology into the Host System Interface electronics bringing their technology as close to a de Facto standard as one could imagine.
An interesting aside is that Ben Vogoda, CEO and Founder, was available after his evening arrival on Wednesday night. By Thursday morning he was solidly booked. LDPC is one application out of many that can be addressed by Lyric’s technology. I expect many more to follow.
Flash, NAND, NOR, SSD, Solid State Drive, Noisy Communications Channel, ECC, Error Checking and Correcting, Apple, Enterprise, PCIe, PCIe SSD, PCIe Storage, PCI Express, DRAM, HDD, Hard Disk Drive, Viterbi, Hamming, Reed-Solomon, BCH, Turbo code, Low Density Parity Code, LDPC, SLC, MLC, TLC, Lyric, Lyric Semiconductor, Ben Vogoda, EZ Flash, ONFI, ONFI Specification, DARPA, Bayesian Network, Stata Venture Partners, Ray Stata, Analog Devices, Host System Interface
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