The Road to 20nm: It Ain't as Easy as it Looks
1/21/2011 by: Darleen Hartley
As the industry adopts 32/28nm technology, the Common Platform development teams aren’t letting grass grow under their feet. The next generation of mobile computing will utilize 20nm. However, climbing Mt Everest might present less challenges than scaling down one more step from today’s norm.
Features are going in opposite directions - performance up, power down. Consumers want their devices to do more, go faster, but without increasing power consumption. The criteria requires novel transistor scaling techniques and highly integrated lithography/design collaboration. Advances in transistor device engineering, extended immersion lithography in the 20nm node, and further development of EUV Lithography [Extreme UltraViolet] are on the table.
Dr. DK Sohn, VP of the R&D Center at Samsung Electronics presented 20nm Technology for Advanced Mobile Computing Tuesday morning at the Common Platform Technology Forum. Samsung is predicting PDK and MPW Shuttle in 2011, risk production in second half of 2012, followed by early production in first quarter of 2013.
Some of the challenges being faced are patterning technologies and source mask optimization [SMO]. SMO could be the path to improving patterning capability. According to Sohn, pitches below 80nm "enter the region where serious innovation is required." 28nm is the last optical shrink half node. Sohn says there is "no direct shrink migration path from 28nm to 20nm. The MOL and contacting scheme is fundamentally different."
The metal–oxide–semiconductor field-effect transistor [MOSFET] is a device used for amplifying or switching electronic signals. The speaker indicated that the status of current silicon shows that: nFET [negative channel field] performance is 85 percent of the current target, whereas pFET [positive channel field] performance has already achieved the current target. The principle of field-effect transistors [FET] was first patented by Julius Edgar Lilienfeld in 1925. Several patent applications such as the one for Mobility Enhanced FET Devices can be found on the Internet.
At 20nm, the industry is looking for performance boosters, stress enhanced performance, and to control the tradeoff between channel mobility enhancement and device leakage.
Sohn indicated that the 20nm LP [low power] device target is delivering industry leading performance, while maintaining competitive speed with low cost. He said "The Common Platform Alliance will continue to collaborate with each company’s R&D teams as one company to deliver robust and manufactureable process technology."
Pictured above: IBM's Watson Research Center
Tags:
DK Sohn, Samsung Electronics, 28nm, 20nm Julius Edgar Lilienfeld, nFET, pFET, MOSFET, EVU, lithography, SMO, source mask optimization, Common Platform, GlobalFoundries, IBM, Chartered, Samsung, Samsung electronics,
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